Search - vhdl uart

[VHDL-FPGA-Verilog] UART

Description: 串行接口UART的用VHDL语言的简单实现，希望对大家有帮助-UART serial interface of the VHDL language with the simple realization, in the hope that everyone has to help
Platform: | Size: 3072 | Author: wangyd | Hits:

[VHDL-FPGA-Verilog] UART

Description: VHDL实现UART通信,包括发送和接叫程序，使用方便-VHDL realize UART communications, including sending and then call the procedure, ease of use
Platform: | Size: 8192 | Author: fdf | Hits:

[VHDL-FPGA-Verilog] uart

Description: M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Platform: | Size: 18432 | Author: lc | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
Platform: | Size: 5093376 | Author: 吕常智 | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 在ＶＨＤＬ上编写了UART通信协议，对于ＦＰＧＡ开发有很大帮助-In VHDL on the preparation of a UART communication protocol, for FPGA development of great help
Platform: | Size: 143360 | Author: 王忠 | Hits:

[Other] u-uart

Description: UART verilog TX/RX OpenCores share
Platform: | Size: 5120 | Author: richman | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 基于FPGA的UART实现用VHDL编程-The UART-based FPGA using VHDL Programming
Platform: | Size: 524288 | Author: hyj1954 | Hits:

[VHDL-FPGA-Verilog] uart

Description: VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过-VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
Platform: | Size: 223232 | Author: 李特威 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
Platform: | Size: 587776 | Author: 李欣 | Hits:

[Embeded-SCM Develop] UART.ZIP

Description: 一个完整的用cpld实现串口功能的代码。经过验证，不经过任何修改便可使用。-serial port realized by vhdl.It has been tested and can be used with any change.
Platform: | Size: 56320 | Author: wangyilong | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART通信协议的硬件描述语言代码，用与FPGA的总线接口开发-UART communication protocol of the hardware description language code, using the bus interface with the FPGA development
Platform: | Size: 22528 | Author: shigengxin | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus
Platform: | Size: 212992 | Author: Carlin | Hits:

[VHDL-FPGA-Verilog] UART

Description: UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧,实现的UART功能稳定、可靠. -UART is a widely used short-range, low-speed, low-cost serial transmission interface communication. Because of the complexity of common UART chip and poor transplant, using a programmable FPGA devices to achieve UART way of the realization of the UART modular design. First of all, a brief introduction of the basic characteristics of UART, and then according to their top-level module system design, and then the design of finite state machine receiver module and transmitter module, the realization of all the features to describe the use of VHDL and Modelsim software used Simulation of all modules. Finally, the UART core functionality into the FPGA, so that the overall design of compact, compact, the UART function of the realization of stable and reliable.
Platform: | Size: 38912 | Author: 徐明宝 | Hits:

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[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart(Verilog)

[VHDL-FPGA-Verilog] UART

[Other] u-uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[Com Port] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[Embeded-SCM Develop] UART.ZIP

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

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